A computer system includes a set of interconnected components or modules of three basic types: central processing unit (CPU), memory, and input/output (I/O). The modules of the computer system are connected together by communication pathways known as busses. A bus is a shared transmission medium in that plural computer modules can transmit across the same bus. However, if two modules transmit during the same time period, their signals will overlap and become garbled. Therefore, it is important to ensure that only one module transmits across the bus during a given time period.
The process of allocating time or bandwidth on a computer bus among plural bus requesters is known as arbitration. Typically, an arbiter grants access for a predetermined time period or bandwidth window to whichever bus requester first requests use of the bus. If plural bus requesters have requests for use of the bus pending, then the arbiter typically employs a rotational priority or round-robin scheme to share the bus among the bus requesters. In a rotational priority scheme, the use of the bus is given for one bandwidth window to each bus requester in sequential order. After the last bus requester uses the bus, then the use of the bus is given back to the first bus requester and the rotational sequence continues.
In many computer systems, such as the Intel P6 computer system, the bus requesters can be either standard bus requesters or priority bus requesters. As the name suggests, bus requests from the priority bus requesters have preference over any new bus requests from the standard bus requesters. In the Intel P6 computer system, from one to four P6 processors are coupled to a processor bus with each P6 processor being a standard bus requester. In addition, one or more bus controllers couple memory and input/output (I/O) devices to the processor bus with each bus controller being a priority requester. The P6 processors are referred to as symmetric bus requesters because they are arbitrated on a strict rotational priority scheme.
Prior art computer systems that include standard and priority bus requesters typically employ some system for ensuring that the priority bus requesters do not completely block the standard bus requesters from using the bus. Such prior art systems assign a predetermined amount of bus bandwidth to the lower priority standard bus requesters. A problem with such a scheme is that the predetermined amount of bus bandwidth is assigned to the lower priority bus requesters regardless of whether they actually need such bus bandwidth. For example, many applications require extensive processor interaction with the processor bus while some applications require much more interaction between the I/O devices and the processor bus. As such, such prior art systems typically assign a predetermined compromise value that is likely to be suboptimal for both types of applications.